A conventional output circuit for a semiconductor integration circuit is shown in FIG. 8. This conventional output circuit will be described below using FIG. 8.
The conventional output circuit is comprised of a signal input terminal 1, an enable signal terminal 2, an inverter 3, a 2-input NAND circuit 4, a 2-input NOR circuit 5, a PMOS transistor P1, an NMOS transistor N1, a power supply terminal 6 supplied with a 3V power supply potential, a ground terminal 7 supplied with a ground potential, and an output terminal 8.
Signal input terminal 1 is connected to one input terminal of each of the 2-input NAND circuit 4 and the 2-input NOR circuit 5. The enable signal input terminal 2 is connected to the other input terminal of the 2-input NAND circuit 4 and the input terminal of the inverter circuit 3. The output terminal of the inverter circuit 3 is connected to the other input terminal of the 2-input NOR circuit 5. The output terminal of the 2-input NAND circuit 4 is connected to the gate electrode of the PMOS transistor P1, while the output terminal of the 2-input NOR circuit 5 is connected to the gate electrode of the NMOS transistor N1. The PMOS transistor P1 is connected between the power supply terminal 6 (3V) and the output terminal 8. The N-well in the substrate of the PMOS transistor P1 is connected to the 3V power supply terminal 6. The NMOS transistor N1 is connected between the ground terminal 7 and the output terminal 8, while the substrate of NMOS transistor N1 (P-well) is connected to the ground terminal 7.
The operation of this circuit will now be described. First of all, when an `L` level signal (0V) is input to the enable signal input terminal 2 as an input signal, the output of the 2-input NAND circuit 4 becomes an `H` level and the output of the 2-input NOR circuit 5 becomes an `L` level. Accordingly, the PMOS transistor P1 and the NMOS transistor N1 are turned off. As a result of this, the output terminal 8 is in a floating state totally unrelated to an input signal to the signal input terminal 1.
Next, when an `H` level signal is input to the enable signal input terminal 2 as an input signal, if an `L` level signal is input to the signal input terminal 1 the PMOS transistor P1 is turned off and the NMOS transistor N1 is turned on. As a result, the output terminal 8 outputs an `L` level signal. On the other hand, if an `H` level signal is input to the signal input terminal 1, the PMOS transistor P1 is turned on and the NMOS transistor N1 is turned off. As a result, the output terminal 8 outputs an `H` level signal.
However, in the conventional output circuit such as that in FIG. 8, when the output terminal 8 is connected to an external element having a power supply voltage higher than 3V, for example a bus etc. supplying signals of 5V, there are circumstances in which the 5V voltage can be applied to the output terminal 8 while the output terminal 8 is in the floating state. If a 5V voltage is applied to the output terminal 8, the drain (P active) of the PMOS transistor P1 becomes 5V. Because the substrate (N-well) of this PMOS transistor P1 is connected to the 3V power supply terminal 6, the diode across the drain (P active) and the substrate (N-well) is forward biased, and so current flows in this diode across the drain and the substrate. This means that if a voltage of 5V is applied to the output terminal 8 due to the influence of the bus etc. having a 5V signal supplied to it, there is a possibility of leakage current of a number of mA flowing in the path from the bus supplied with a 5V signal, to the output terminal 8, to the drain of the PMOS transistor P1, to the substrate of the PMOS transistor P1, to power supply terminal 6 of the output circuit. The object of the present invention is to improve this problem.